1. Field of the Invention
The present invention relates to improvements in a semiconductor reference voltage generators and, more particularly, to improvements in reference voltage generators used in electrically erasable, electrically programmable, read-only memories.
2. Description of the Related Art
Recently, a new type single-transistor non-volatile memory cell device has been proposed that uses a biased reference potential, one that is different from the system ground, to minimize disturbs and column leakage during read operations. Higher storage capacity and lower costs are achieved by utilizing a smaller memory cell of the type having a single memory transistor which shares its source and drain nodes with adjacent memory cells within a column. Several such cells are grouped together to form either a NAND array, a NOR array, or an AND array, with means to connect separate points within the array to bit lines and to the generated reference potential.
FIG. 1 shows a non-volatile memory device according to prior art that applies the reference potential directly to nodes within the memory cell array. It includes at least one block 95, blocks 0 through m being shown. Each block 95 contains an array of addressable single transistor memory cells. Two embodiments of the array of memory cells within the blocks 95 in FIG. 1 are described below. Associated with each block 95 are the row decoders 92 that drive lines 801, which span the width of the blocks 95. The use of these lines 801 within block 95 is described in greater detail below. The blocks 95 are linked together by the bit lines 800 that also go to the page sense amplifiers, buffers and column decoders 94. Further, blocks 95 are linked together in common by common source line (CSL) 810 which forms a common reference node whose voltage is generated and controlled by reference generator 96. Reference generator 96 is required since the voltage on the CSL is not equal to ground potential during read modes as will be described in detail later.
Predecoded row address selection information is supplied to row decoders 92 by the row predecoders 91 by way of the predecoded row address bus 803. Row address lines 802 supply row input address information to row predecoders 91 and likewise column address lines 804 provide column input address information to column decoders included in 94. An erase/program control unit 93 is included which is controlled by write control lines 809 to supply Vneg1 806 to the row decoders 92, Vneg2 808 to the page sense amps, buffers and column decoders unit 94, and Vpw 807 to the memory array 90. Data input and output is performed by way of data line 805.
FIG. 2 shows a second non-volatile memory device according to prior art that applies the reference potential to nodes within the array by way of a decoded path. Non-volatile memory cells are arranged in a plurality of columns and rows of identical cells to form a cell array 95'. Two embodiments of the array of memory cells within the block 95' in FIG. 2 are described below.
As schematically shown in FIG. 2, the output, Vrout, of the reference generator 267 is connected through select circuits 261 and 263 to virtual ground lines and bit lines, designated as VG and BL respectively. The bit lines BL0, BL1, . . . BLn, and virtual ground lines VG0, VG1, . . . VGn, of the array are addressed by signals from a Y-decoder 263, which decodes address signals applied to an input address bus 264. The current produced on the bit lines BL0, BL1, . . . BLn during a read operation is sensed by a sense amplifier 268 for delivery to an output terminal 269, while the virtual ground lines VG0, VG1, . . . VGn are held at the on-chip generated reference potential, Vr, from reference generator 267.
In like manner, the gate lines SG0, SG1, . . . SGn are addressed by signals from an X-decoder 265, which decodes address signals applied to an input address bus 266. The X- and Y-decoders 265 and 263 each receive a on-chip generated reference voltage, Vr, from reference voltage generator 267, a supply voltage Vcc, a supply reference potential Vss, and a programming voltage Vpp for selective application to the respective bit, virtual ground, gate lines, and substrate of the array 95', as well as read, erase, and program control signals to specify the particular function to be performed and voltage levels to be selected and applied.
The construction of the reference voltage generator 96 in FIG. 1 and 267 in FIG. 2 has been previously described as a voltage divider, band gap, or other similar circuit. A new type of reference voltage generator is the subject of this invention.
FIG. 3 shows a NAND cell array 96 according to the prior art that can be placed within memory block 95 in FIG. 1 or memory block 95' of FIG. 2. Read biases for block 96 are shown in the associated table. Block 96 includes (n+1) copies of the NAND stack 40, each of which is connected at the top to one of (n+1) bit lines, BL0, BL1, through BLn and connected on the bottom to the common source line CSL. Further, the entire block 96 resides within a common well connected to Vpw. In FIG. 3 sixteen non-volatile memory transistors 10, labeled MC0, MC1, through MC15, are shown in each NAND stack 40.
The gates of transistors MC0, MC1, through MC15 are connected in common with gates of adjacent NAND stacks within block 96 by way of word lines WL0, WL1, through WL15, respectively. Except for memory transistors MC0 and MC15, the drain and source of adjacent memory cells within the NAND stack 40 are connected together. The source of memory transistor MC0 is connected to the drain of the next memory cell down, memory transistor MC1. Also, the drain of memory transistor MC0 is connected to a bit line (BL). The drain of memory transistor MC15 is connected to the source of the next memory cell above, memory transistor MC14. Also, the source of memory transistor MC15 is connected to the drain of select transistor MSS and the source of select transistor MSS is connected to the common reference line (CSL), which is typically a diffusion. The NAND stack 40 also includes a selection transistor MSS whose gate is connected in common with adjacent NAND stacks within block 96 by way of the global select line, GSL0.
Memory transistor 10 is an insulated gate field effect transistor that includes a charge storage layer 32 embedded in its gate dielectric, as shown in FIG. 4. The charge storage layer 32 is typically surrounded by at least a top dielectric 31 and a bottom dielectric 33 and resides between the gate 12 and the channel 15 of the transistor. Channel 15 resides in the silicon bulk 11 between the source 14 and drain 16 regions. The charge storage layer 32 is either a "floating gate" of conductive material, typically of doped polycrystalline silicon, or a dielectric material such as silicon nitride, silicon oxynitride, silicon-rich silicon dioxide, or a ferroelectric material.
The amount and polarity of charge residing in the charge storage layer strongly affects the conductivity of the transistor 10. The words "programmed" and "erased" are used to describe two possible conductivity states that a transistor can achieve under two different charge storage conditions. It is recognized that the designation of the words "programmed" and "erased" is purely arbitrary and that these terms are selected to represent opposite meanings depending on the application. Here the terms are consistently used in reference to the relative levels of conductance. Thus the terms "erased" and "programmed" are used to describe the "on" and "off" states, respectively. The primary difference between these two states is the level of conductance in transistor 10 while under read biases. An "on" state results when the transistor 10 is conductive and an "off" state results when the transistor 10 is non-conductive, or at least is less conductive than a predetermined range of conductance that represents the "on" state.
Referring additionally to the table in FIG. 3, the NAND stack utilizes a read bias scheme in which Vr is supplied to the source side of the NAND stack by way of CSL. Gates of unselected memory cells are placed at Vg,on which is at least equal in magnitude to the magnitude of Vr plus the maximum program state threshold voltage (Vr+Vtpmax). The selected memory cell gate is biased at the well potential, in this case Vs=ground.
With the gate of the selected memory cell at 0 volts and the program threshold voltage negative, the common reference line, CSL, needs to be biased above the gate potential to turn off a selected cell when it is programmed. The voltage relative to the well on the common reference line, CSL, necessary to turn off selected programmed memory cells is Vr, and is described by .vertline.Vtpmin.vertline.&lt;Vr&lt;.vertline.Vtemax.vertline.. With the values of Vtpmin=-1.5 volts and Vtemax=-2.0 volts, the value of Vr could be 1.8 volts.
More specifically, when reading the state of transistor MC1, word line WL1 is placed at the well potential, in this case Vs=ground, while all other word lines are at Vg,on, in this case chosen to be Vcc, rendering them conductive. Further, common reference line, CSL, is at Vr=1.8 volts and the bit line potential on BL0 is placed at Vcc. If memory transistor MC1 is erased with a depletion threshold voltage of magnitude greater than Vr, memory transistor MC1 will be conductive, allowing current flow through the NAND stack. The potential of the bit line, BL, will fall from Vcc toward Vr. If memory transistor MC1 is programmed with a depletion threshold voltage of magnitude less than Vr, memory transistor MC1 will be non-conductive, impeding current flow through the NAND stack. The potential of the bit line, BL, will remain equal or nearly equal to Vcc. The state of the selected cell is determined by sensing the voltage on the bit line, BL, using conventional sensing means.
FIG. 5 shows a NOR cell array 97 according to the prior art which can be placed within memory block 95 in FIG. 1 or memory block 95' of FIG. 2. Read biases for block 97 are shown in the associated table. As schematically shown in FIG. 5, the block 97 includes an array of memory cells 10 as shown in FIG. 4. The cells 10' and 10'" are connected at the source nodes 14' and 14'" to the virtual ground line 252, designated as VG0, and the source nodes 14" and 14"" of cells 10" and 10"" are connected to the virtual ground line 253, designated as VG1. Likewise, the drain nodes 16' and 16'" of the cells 10' and 10'" are connected the bit line 251, designated as BL0, and the drain nodes 16" and 16"" of the cells 10" and 10"" are connected to bit line 254, designated as BL1.
The cells 10' and 10" share a common gate line 259 (SG0), and cells 10'" and 10"" share a common gate line 260 (SG1). Simply stated, the drain nodes 16 and source nodes 14 are "shared" among the cells 10 in columns and the gate nodes 12 are "shared" among the cells 10 in rows. Since the source nodes 14 and drain nodes 16 are not "shared" among cells 10 in any row, independent control of source lines is possible, permitting unaddressed cells to be actively deselected for elimination of high currents and "disturbed" cells.
On the other hand, cells 10 with "shared" or common drain nodes 16 and source nodes 14 have separates gate nodes 12 permitting a single addressed cell 10 to be read. Of course, an entire row of cells 10 can be read if desired.
Referring additionally to the table included in FIG. 5, the cell array 97 can be read by sensing a current on the bit lines 251, 254 or the virtual ground lines 252, 253 by known sensing techniques.
A cell 10 is read by the application of a voltage difference between the drain 16 and source 14, while the gate 12 is biased positive with respect to the bulk node 11 (or P-well) by an amount V.sub.r, with the gate-to-source potential difference remaining zero. An erased device has a negative threshold voltage, so when its gate and source potential are equal at V.sub.r, the erased device will be "on" and conducting current. A programmed device has a positive threshold voltage, so when its gate and source potential are equal at V.sub.r, the programmed device will be "off" and non-conducting. The logic state of the cell 10 may be determined by using known sensing circuitry to measure the channel current of cell 10 under the bias conditions described in the prior sentence.
More specifically, when reading cells 0 and 1 in NOR cell array 97, the bulk is biased to the supply reference potential, Vss. The supply voltage, Vcc, is applied to the bitlines BL0 and BL1, while the on-chip generated reference potential, Vr, is applied to the virtual ground lines, VG0 and VG1. The gate of selected cells 0 and 1, SG0, is placed at Vr and the gate of unselected cells 2 and 3, SG1, is placed at Vss. With the gate to source voltage at zero on selected cells 0 and 1, current is expected to flow through these devices if they are erased. Since the voltage difference between the gate and source of the unselected cells 2 and 3 is negative by and amount Vr, the unselected cells will conduct little or no current compared to the erase current expected to flow in cells 0 and 1. The selection of the value of Vr is determined by the total current flow expected through the unselected cells. Vr must be sufficiently large to make this "leakage" current much less than the "on" current of erased selected cells.
One of the advantages provided by this circuit is that the value of V.sub.r is less than V.sub.cc. It has been found that by using gate selection on a cell by bringing the source potential up from the potential of the substrate to a value V.sub.r, the device can be deselected by bringing the gate potential from V.sub.r to V.sub.ss, thereby turning off the source junction, and, consequently, creating no fields between the gate the substrate that may cause a disturb condition. The purpose of V.sub.r is also to allow the method or system of reading individual cells in a cell array without causing a disturb to the cells of the array, and particularly to the addressed cell(s).
The upper limit of the magnitude of the value of V.sub.r should be selected to be less than V.sub.cc, and preferably less than V.sub.cc -V.sub.ds,sat, where V.sub.ds,sat is the saturation voltage of the device. Since the voltage on the drain of a cell being read is V.sub.cc, the value of V.sub.r on the source and gate should be selected to still enable sufficient current to flow to be detectable. Moreover, the erase threshold can change with age (typically becoming less negative). Cells which have been cycled a large number of times or which contain older data produce different (typically less) current levels when addressed compared to uncycled cells containing freshly written data. Thus, the upper limit that can be selected for V.sub.r needs to take both beginning-of-life and end-of-life current levels into consideration. Preferably, V.sub.r should be selected to be as close to the magnitude of the threshold of an erased cell as possible, allowing sufficient current to flow for reliable sensing under end of life conditions.
In prior art, the reference generator, which produces Vr, has typically been of the type that does not take into account the changes in erased threshold voltage as a function of time or use. Typically, the reference generator produces a voltage that is derived from a reference source and the output of the reference voltage generator is controlled through a negative feedback system.
FIG. 6 shows a schematic of a typical reference voltage generator 60. A power source 61 supplies power at a voltage higher than the reference voltage, Vr, to be produced at node 67. Within an integrated circuit, the power supply typically provides Vcc and the power source reference potential, typically Vss. A reference source 62 generates Vref on node 66, which is provided to the non-inverting input of a differential amplifier 63. Amplifier 63 produces Vr at its output and provides current gain to drive the reference generator output 67. Negative feedback of the output voltage, Vr, is provided by a voltage feedback circuit 64, the output of which is supplied to the inverting input of differential amplifier 63 at node 65. Voltage feedback circuit 64 generates an output, Vf, which is a function of Vr, typically a fixed offset from Vr, a ratio multiplied by Vr or some combination of both. The negative feedback serves to drive the output of amplifier 63 to Vr when Vf is equal or nearly equal to Vref. One aspect of this invention is to provide a new and improved circuit for the reference source 62 that is useful for the memory circuit applications shown in FIG. 1 and FIG. 2 above.
Examples of prior art reference source circuits are resistor or capacitor voltage dividers, biased diode dividers such as used in band gap references or Zener diode reference circuits, as shown in FIG. 7. Another example shown in FIG. 7 is a transistor-based, push-pull amplifier-like, reference voltage generator as used in DRAM products.
All such voltage reference sources are typically designed to provide a fixed voltage output which, when placed in a reference generator circuit such as the one shown in FIG. 5, is insensitive to natural variations in temperature, power-source voltage, device geometry, current load on the output, and others. This is a suitable design criterion when the operation of the device for which the reference voltage is supplied operates best when the voltage is independent of these expected variations.
However, this criterion is not proper for the reference voltage needs described above for the non-volatile memory arrays in FIG. 3 and FIG. 5. In particular, it is desirable for optimal operation of the arrays shown in FIG. 3 and FIG. 5 to change the reference voltage with variations, rather than hold it fixed. This criterion is best understood by examining the use of Vr during the read operations of the arrays in FIG. 3 and FIG. 5.
A primary objective in placing Vr on the source side of the memory array transistors in FIG. 3 and FIG. 5 is to ensure that the devices which are expected to turn off during a read operation will be sufficiently non-conductive when their gate voltage is set to the well potential (typically Vss). These "off" devices must conduct little or no current in comparison to those devices that are expected to turn "on" in order to accurately determine the logic state of selected devices throughout a wide range of operating conditions.
In the case of the array shown in FIG. 3, Vr must be sufficient enough to ensure that the selected device, the gate of which is set to the well potential, is in a low conductance state, passing little or no current, when in the program state. Likewise, for the array shown in FIG. 5, Vr must be sufficient enough to ensure that the deselected devices, the gate of which are set to the well potential, are in the low conductance state, passing little or no current during a read operation.
The conductivity a non-volatile memory transistor under a fixed bias condition depends on a number of parameters. These include the transistor channel length and width, the transistor temperature, the doping in the transistor channel, the dielectric thickness between the channel and the gate, the amount of charge stored in the charge storage element, the effects of repeatedly cycling the transistor from one state to another, and others. Further, the output of a voltage generator tends to vary with several of these parameters, and often times does so independently of variations in the non-volatile memory transistor conductivity.
In order to achieve and maintain consistent performance independent of these variations, the reference potential, Vr, must be generated in a way that it ensures a maximum "off" current regardless of variations in the parameters that affect the non-volatile memory transistor conductivity. Since the reference voltage generator is typically designed to provide a constant voltage output, extra margins are typically included in the selection of Vr in order to accommodate expected variations in operating conditions and transistor structure. Alternately, it is desirable to generate Vr using a reference source that tracks these variations rather than not, ensuring a constant "off" current, rather than a constant voltage, under all expected variations.
By using a reference source that tracks variations that affect non-volatile memory transistor conductivity, there is little or no need to select and control Vr in a manner that incorporates extra margins. Eliminating extra margins in Vr positively affects performance of devices shown in FIG. 1 and FIG. 2. As Vr decreases in magnitude, the drive current on devices that are in the "on" state increases. Thus, it is desirable to provide a reference source that is set to just eliminate conduction in "off" devices, and which tracks variations in order to ensure that such devices remain off under all expected operating conditions and variations.
Therefore, without further innovation the low cost advantages of the single transistor memory cell devices described above cannot be fully realized without a reference voltage generator that tracks variations in the construction, history and operation of the non-volatile transistors within the memory array.